Android 10.0.0_2.5.0 - mPCIE - Modem¶

Overview¶

The DART-MX8M-PLUS is capable of adding a Mini PCI-E based modem to support LTE connectivity.

Note:

At present we support LTE Quectel EC25.
Other modules could be supported please contact your module vendor.
Below steps are validated and tested upto Android 11 version.

Hardware Interface¶

Quectel EC25 mPCI-E Hardware module with a SIM card.
mPCI-E interface with USB support, like the one on the DT8MCustomBoard (note that the Symphony-Board mPCI-E interface does not support USB).

Hardware Availability and Setup¶

Connect SIM card to mPCIe-E module.
Connect mPCI-E Module to J23.

Note: Make sure your SIM provider is supporting mPCI-E module specification of the network.

Software Setup¶

Make sure you have the required hardware as per above.

RIL Setup¶

By default, the build doesn't have a RIL setup.
To add the RIL support follow the below steps.

Register and get access to the download zone https://www.quectel.com/login
Download Quectel_Android_RIL_Driver_XX.Y.ZZ_master_.tgz
Where (XX.Y.ZZ are version numbers from quectel and can be alpha/beta etc)

Adding Driver to build¶

Edit imx8_var_android_defconfig and enable following

Device Drivers->
 Network device support ->
  USB Network Adapters ->
   Multi-purpose USB Networking Framework ->
    <*> QMI WWAN driver for Qualcomm MSM based 3G and LTE modems

and enable following config:

CONFIG_USB_NET_QMI_WWAN=y

Downloading and adding Quectel RIL to build¶

$ cd ~/var_imx-android-10.0.0_2.5.0/android_build
$ mkdir -p vendor/quectel/
$ tar -xvf ~/Downloads/Quectel_Android_RIL_Driver_V3.3.49_master_beta.tgz -C vendor/quectel/

Add Quectel libraries to build¶

Edit device/variscite/imx8m/dart_mx8mp/dart_mx8mp.mk and add following code

TARGET_HAVE_QUECTEL_RIL := true 
ifeq ($(TARGET_HAVE_QUECTEL_RIL),true)
# wifionly device
PRODUCT_PROPERTY_OVERRIDES += \
    ro.radio.noril=false

PRODUCT_COPY_FILES += \
    vendor/quectel/libquectel-ril/arm64-v8a/libreference-ril.so:vendor/lib64/hw/libreferece-ril.so \
    vendor/quectel/libquectel-ril/arm64-v8a/ip-up:vendor/bin/ip-up \ 
    vendor/quectel/libquectel-ril/arm64-v8a/chat:vendor/bin/chat \
    vendor/quectel/libquectel-ril/arm64-v8a/ip-down:vendor/bin/ip-down \
    vendor/quectel/libquectel-ril/ql-ril.conf:vendor/etc/ql-ril.conf
fi

Add Quectel libraries in the ril-daemon service¶

Edit device/variscite/imx8m/dart_mx8mp/init.rc and add following code

service ril-daemon /vendor/bin/hw/rild -l vendor/lib64/hw/
    class main
    user radio
    group radio cache inet misc audio sdcard_rw log
    capabilities BLOCK_SUSPEND NET_ADMIN NET_RAW

Add RILD in the HIDL service¶

Edit device/variscite/imx8m/dart_mx8mp/manifest.xml and add following code

<hal format="hidl">
    <name>android.hardware.radio</name>
    <transport>hwbinder</transport>
    <fqname>@1.4::IRadio/slot1</fqname>
    <fqname>@1.2::ISap/slot1</fqname>
</hal>

Setup file context and selinux permissions¶

Edit device/variscite/imx8m/dart_mx8mp/ueventd.nxp.rc and add following code

#quectel port
/dev/ttyUSB* 0660 radio radio
/dev/ttyACM* 0660 radio radio
/dev/cdc-wdm* 0660 radio radio
/dev/qcqmi* 0660 radio radio
/dev/cdc-acm* 0660 radio radio
#PCIe
/dev/mhi_DUN 0660 radio radio
/dev/mhi_DIAG 0660 radio radio
/dev/mhi_BHI 0660 radio radio
/dev/mhi_LOOPBACK 0660 radio radio
/dev/mhi_QMI0 0660 radio radio

Edit device/variscite/imx8m/dart_mx8mp/sepolicy/file_contexts and add following code

#quectel
/dev/ttyUSB[0-9] u:object_r:radio_device:s0
/dev/ttyACM[0-9] u:object_r:radio_device:s0
/dev/cdc-wdm[0-9] u:object_r:radio_device:s0
/dev/qcqmi[0-9] u:object_r:radio_device:s0
/vendor/bin/hw/rild u:object_r:rild_exec:s0
/dev/socket/rildOemHook u:object_r:rild_socket:s0
#PCIe
/dev/mhi_DUN u:object_r:radio_device:s0
/dev/mhi_DIAG u:object_r:radio_device:s0
/dev/mhi_BHI u:object_r:radio_device:s0
/dev/mhi_LOOPBACK u:object_r:radio_device:s0
/dev/mhi_QMI0 u:object_r:radio_device:s0

Create a seplicy file for rild to allow the socket communication File : device/variscite/imx8m/dart_mx8mp/sepolicy/rild.te and add the following content to it.

allow rild self:packet_socket { create bind write read };