SPI¶

In this example we will show how to configure and test SPI1 on DART-MX8M-PLUS. The SPI pins on external connector J16 are used for SPI loopback test.

Kernel configuration¶

Verify that the i.MX SPI driver (CONFIG_SPI_IMX) is enabled in your kernel configuration:

In menuconfig: Device Drivers -> SPI support -> <*> Freescale i.MX SPI controllers

Verify that the User mode SPI driver (CONFIG_SPI_SPIDEV) is enabled in your kernel configuration:

In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support

Device Tree configuration¶

The default DART-MX8M-PLUS SPI configuration is for resistive touch controller on CS0. For the purpose of loop back test the configuration should be modified to use a different CS line.

Add spidev node¶

Edit /arch/arm64/boot/dts/freescale/imx8mp-var-smarc-echo.dts to modify cs-gpios property and add spidev node.
GPIO1_12 will be used in this example to control SPI CS0.

&ecspi1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_ecspi1>;
        cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
    status = "okay";

        spidev@0 {
               compatible = "spidev";
               spi-max-frequency = <12000000>;
               reg = <0>;
        };
};

Configure SPI1 pins¶

&iomuxc {
    ...
    pinctrl_ecspi1: ecspi1grp {
        fsl,pins = <
            MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK              0x12
            MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI              0x12
            MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO              0x12
            MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17               0x12
        >;
    };
    ...
};

Recompile the kernel¶

Compile the kernel (only if kernel configuration was changed) and device tree and update the SOM.

Compile SPI test application¶

There's an SPI test utility in the kernel source tree: tools/spi/spidev_test.c
To cross compile it, use the following command:

$ $CC ./tools/spi/spidev_test.c -o ./spidev_test

SPI 1 External Connector¶

SPI 1 will be accessible on the following EVK pins:

J6.9 - SPI1.SS0
J6.11 - SPI1.SCLK
J6.13 - SPI1.MOSI
J6.15 - SPI1.MISO

Run SPI Test¶

Copy spidev_test binary to VAR-SMARC-MX8M-PLUS.
Loop SPI1.MOSI and SPI1.MISO by putting a jumper on J6.13 and J6.15

Run SPI test tool

# ./spidev_test -v -D /dev/spidev0.0

The output of successful test should look like this:

spi mode: 0x20
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.
RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.

Using multiple SPI CS lines¶

The i.MX8M-PLUS SPI controllers support up to 4 chip select lines.

In the example below GPIO1_12 and GPIO1_15 are used to control CS0 and CS1 respectively.
When selecting CS GPIO pins make sure they are not used to control other peripherals.

&ecspi1 {
    #address-cells = <1>;
    #size-cells = <0>;
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_ecspi1>;
            MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17               0x12

        cs-gpios = <&gpio5 17 0>,
                   <&gpio5 13 0>;
        fsl,spi-num-chipselects = <2>;
    status = "okay";

        chip1@0 {
               reg = <0>;
               ...
        };

        chip2@1 {
               reg = <1>;
               ...
        };
};

&iomuxc {
    ...
    pinctrl_ecspi1: ecspi1grp {
        fsl,pins = <
            MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK              0x12
            MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI              0x12
            MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO              0x12
            MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17               0x12
            MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13             0x12
        >;
    };
    ...
};